Location: On-site in Santa Clara, CA
Job Type: Full-Time
Company: Upscale AI
Team Size: +100 employees
Industry: High-Tech / Emerging Infrastructure
Job Title : Senior Design Verification Engineer
Why join Upscale AI
Upscale ai is an innovative high-tech startup delivering breakthrough infrastructure solutions in AI. With a rapidly growing team and cutting-edge stack, we’re building for scale, resilience, and productivity. We’re looking for a smart, driven engineering professional to join our infrastructure team and help support a secure, scalable, and user-friendly computing environment across the company.
Job Responsibilities
- Architect and develop verification environment, testbench components, and reference models for designs at block and system level.
- Develop a comprehensive test plan and implement test cases.
- Verify design in block and chip-level environments using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification.
- Perform RTL code coverage, assertion coverage, and gate-level simulations.
- Drive and adopt new verification methodologies and flows for efficiency improvements.
Job Requirements
- BS in Electrical Engineering, Computer Science, or related field with 15+ years of Industry experience or MS in Electrical Engineering, Computer Science, or related field preferred with 12+ years industry experience.
- Experience in verifying designs at block and system level.
- Experience using SystemVerilog and UVM.
- Strong experience in ASIC design verification flows and DV methodologies.
- Experience working with cross-functional teams to deliver ASICs from architecture to FCS.
- Strong programming and scripting language (C/C++/Python etc.) capability.
- Strong and independent design debugging capability.
- Domain knowledge of Ethernet, PCIe, and Switch Fabric is desirable.
- Good problem-solving skills and the passion to take on challenges.
- Highly motivated and able to work independently and as a team member.
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