Location: On-site in Santa Clara, CA
Job Type: Full-Time
Company: Upscale AI
Team Size: +100 employees
Industry: High-Tech / Emerging Infrastructure
Why join Upscale AI
You want to be a part of something groundbreaking, where every day you can see the impact of your work. At Upscale AI, you will join a talent-rich group of problem solvers and doers; in a culture that focuses on team, growth, innovation, and creativity. Our goal is to hire and promote an exceptional workforce as diverse as the global populations we serve. Upscale AI is an equal-opportunity employer committed to diversity, inclusion, and belonging in all aspects of our organization. We know that our individual differences make us better.
What you’ll do:
- Lead Top Level Integration: Architect and implement top-level integration for complex networking ASICs, working closely with Chip Leads to define hierarchy and connectivity.
- Block & IP Integration: Take ownership of integrating critical “Top-Level” IPs, including PLLs, PVT sensors, Pad Rings
- Execute and debug front-end quality checks, including LINT, CDC and LEC
- Partner with the Physical Design (PD) team to define top-level floorplanning and routing constraints
- Collaborate with DFT engineers to integrate scan chains, MBIST, and JTAG at the SoC level, ensuring test coverage goals are met.
What you bring:
- Education: BE/BS or MS in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS).
- Experience: 3+ years of industry experience in ASIC/SoC design with a focus on Top-Level Integration.
- Proficiency in SystemVerilog for design
- Hands-on experience with industry-standard tools for Synthesis Lint, CDC and LEC
- Ability to communicate complex technical trade-offs to diverse, cross-functional teams.
Preferred:
- 5+ years of experience with a track record of at least one successful production tapeout at advanced process nodes (7nm or below).
- Solid understanding of Physical Design challenges, including congestion management, feedthrough insertion and top level routing channels
- Knowledge of PLL integration, chip-level clock distribution, and Power-On-Reset (POR) sequencing.
- Basic understanding of DFT requirements for top level RTL integration
- Strong scripting proficiency (Tcl, Python, or Perl) to automate integration tasks and netlist processing.
- Proactive mindset with the ability to thrive and lead in a fast-paced, high-growth environment.
Compensation:
The national pay range for our technical roles is $100,000-$500,000. The national pay range for our non-technical roles is $75,000-$470,000. Individual compensation will be commensurate with the candidate’s experience aligned with Upscale AI’s internal leveling guidelines and benchmarks.
Upscale AI is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.
Upscale AI is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: hiring@upscaleai.com. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.
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